View 73S8009C_5363558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

73S8009C versatile power management and smart card interface ic simplifying system integration ? data sheet ds_8009c_025 febru ary 2010 rev. 1.5 ? 2010 teridi an semiconductor corporation 1 description the teridian 73S8009C is a versatile power management and single smart card interface circuit that is ideally suited for smart card reader products that are battery and/or usb bus - powered. in addition to its emv 4.1 and iso - 7816 - 3 compli ant smart card - to - host interface circuitry; it provides control, conversion, and regulation of power for a companion host processor circuit and power for the smart card. the 73S8009C can operate from a single 2.7 v to 6.5 v source supply, or a combination of battery power (4.0 v to 6.5 v) and usb power (4.4 v to 5.5 v). the 73S8009C supports 5 v, 3 v, and 1.8 v smart cards. the smart card signals for rst, clk, io, and auxiliary signals aux1 and aux2 are level - shifted to the selected v cc value . although the host controller is required to handle the detailed signal timing for activation and de - activation under normal conditions, the 73S8009C blocks any spurious signals on clk, rst and io during power - up (as v cc rises) and power - down. the 73S8009C contains two handshaking signals for the controller: off indicates that a card is present, and rdy indicates that v cc is at an acceptable value. the 73S8009C will perform emergency deactivation upon card removal, voltage faults, or over - current events the power management circuitry of the 73S8009C allows operation from a wide range of voltages from multiple sources. v pc is converted by using an inductive, step - up power converter to the intermediate voltage, v p . v p is used by linear voltage regulators and switc hes to create the voltages v dd and as required, v cc . v dd is used by the 73S8009C and is also made available for the companion controller circuit or other external circuits. the v bat and v bus p ins p rovide inputs from alternate power sources as required. an internal switch in the 73S8009C acts as a single - pole, double - throw switch that selects either v bat or v bus to be connected to v pc . when the voltage on v bus is zero, v bat is connected to v pc . when voltage is applied to v bus , the switch select s v bus as the source for power. when power is supplied by v pc or v bat , the 73S8009C is controlled by the on _ off pin in the manner of a ?push - on/push - off? button action. the off_req and off_ack signals provide handshaking and control of the power ?off? function by the controller. a spst momentary switch to ground connected to on _ off is all that is required for power control. alternatively, the ?off? state can be initiated from the host controller through off_ack. when the 73S8009C is ?off,? the current is less th an 1 a. when power is supplied via the v bus pin, the 73S8009C is unconditionally in the ?power - on? state regardless of the action of the on/off switch or off_ack signal. power supply current operating from the v bus power when v cc is off is less than 500 a to conform to usb ?suspend? requirements. applications ? handheld pinpad smart card readers for e - commer ce, secure login, e - health, gov ?t id and loyalty ? point of sales & transaction terminals ? general purpose smart card readers advantages ? ideally suite d to usb bus - powered applications ? ideal for combo bus - powered and/or self - powered systems ? automatic battery switchover in bus powered systems ? very low - power mode (sub - a) with push - button on/off switch input with de - bounce ? provides 3.3 v / 40 ma power to external circuitry (host processor or peripheral circuits) ? the inductor - based dc - dc converter provides higher current and efficiency than usual charge - pump capacitor - based converters: ? ideal for battery - powered applications
73S8009C data sheet ds_8009c_025 2 rev. 1.5 features ? smart card inter face: ? complies with iso - 7816 - 3 and emv 4.1 and derivative standards ? a dc - dc converter provides 1.8 v/3 v/5 v to the card from a wide range of external power supply inputs ? provides up to 65 ma to the card ? iso - 7816 - 3 card emergency deactivation sequencer ? 2 v oltage supervisors detect voltage drops on the v cc (card) and v dd (digital) power supplies ? card over - current detection 150 ma max. ? 2 card detection inputs, 1 for either user polarity ? auxiliary i/o lines for synchronous and iso - 7816 - 12 usb card support ? car d clk clock frequency up to 20 mhz ? 6 kv esd and short circuit protection on the card interface ? system controller interface: ? 5 signal images of the card signals (rstin, clkin, i / ouc, aux1uc and aux2uc) ? 2 inputs activate and select the card voltage ( cmdvcc% and cmdvcc# ) ? 2 outputs, interrupt to the system controller ( off and rdy), to inform the system controller of the card presence / faults and status of the interface ? 1 chi p select input ? 2 handshaking signals for proper shutdown sequencing of all output sup ply voltages (off_req, off_ack) ? on/off main system switch: ? input for an spst momentary switch to ground ? dc- dc converter: ? step - up converter ? generates an intermediary voltage v p ? requires a single 10 h inductor ? system power supply requirements: ? when using vbus: standard usb +5 input (range +4.4 v to 5.5 v) ? when using v bat : 4.0 v to 6.5 v ? when using v pc : 2.7 v to 6.5 v ? automated detection of voltage presence - priority on vbus over vbat ? power sup ply output: ? v dd supply output available to power up external circuitry: 3.3 v 0.3 v, 40 ma ? industrial temperature range ? small format qf n package ? rohs compliant (6/6) lead - free package
73S8009C data sheet ds_8009c_025 rev. 1.5 3 functional diagram pin numbers reference the qfn32 package . figure 1 : 73S8009C block diagram smart card i / o buffers and signal logic switch / ldo regulator voltage reference control logic reset buffer clock buffer r - c osc . vcc fault vpc fault 1 . 5 mhz vdd vbus vcc rst clk pres pres i / o aux 1 aux 2 clkin i / ouc aux 1 uc aux 2 uc rstin rdy gnd off test 2 bias currents vref gnd vbat vpc lin vcc ok vcc = 3 vcc = 5 power down on / off on _ off s 2 s 1 off_ req off _ ack vp cs test 1 30 10 12 29 25 23 15 26 27 19 18 16 14 13 22 21 20 17 28 3 2 1 7 6 9 11 8 32 5 4 24 cmdvcc 5 cmdvcc 3
73S8009C data sheet ds_8009c_025 4 rev. 1.5 table of contents 1 pinout ............................................................................................................................................. 6 2 electrical specifications .............................................................................................................. 10 2.1 absolute maximum ratings ................................................................................................... 10 2.2 recommended operating conditions .................................................................................... 11 2.3 smart card interface requirements ...................................................................................... 11 2.4 digital signals characteristics ............................................................................................... 14 2.5 dc characteristic s ................................................................................................................ 15 2.6 voltage / temperature fault detection circuits ...................................................................... 15 2.7 thermal characteristics ........................................................................................................ 15 3 applications information ............................................................................................................. 16 3.1 example 73S8009C schematics ........................................................................................... 16 3.2 power supply and converter ................................................................................................. 18 3.3 interface function - on/off modes ...................................................................................... 18 3.4 system controller interface ................................................................................................... 20 3.5 card power supply and voltage supervision ......................................................................... 20 3.6 activation and de - activation sequence ................................................................................. 21 3.7 off and fault detecti on ....................................................................................................... 22 3.8 chip selection ....................................................................................................................... 23 3.9 i/o circuitry and timing ......................................................................................................... 24 4 eq uivalent circuits ...................................................................................................................... 26 5 mechanical drawing .................................................................................................................... 30 6 ordering information ................................................................................................................... 31 7 related documentation ............................................................................................................... 31 8 contact information ..................................................................................................................... 31
ds_8009c_025 73S8009C data sheet rev. 1.5 5 figures figure 1: 73S8009C block diagram ......................................................................................................... 3 figure 2: 73S8009C 32 - pin qfn pinout .................................................................................................. 6 figure 3: typical 73S8009C application schematic ............................................................................... 17 figure 4: 73S8009C logical block diagram ........................................................................................... 19 figure 5: activation sequence ............................................................................................................... 21 figure 6: deactivation sequence ........................................................................................................... 22 figure 7: off activity ............................................................................................................................ 22 figure 8: cs timing definitions .............................................................................................................. 23 figure 9: i/o and i/ouc state diagram .................................................................................................. 24 figure 10: i/o ? i/ouc delays - timing diagram .................................................................................... 25 figure 11: on_off pin ............................................................................................................................ 26 figure 12: open drain type ? off and rdy .......................................................................................... 26 figure 13: power input/output circuit, vdd, lin, vpc, vcc, vp ........................................................... 26 figure 14: smart card clk driver circuit .............................................................................................. 27 figure 15: smart card rst driver circuit .............................................................................................. 27 figure 16: smart card io, aux1, and aux2 interface circuit ................................................................. 28 figure 17: smart card i/ouc, aux1uc and aux2uc interface circuit .................................................. 28 figure 18: general input circuit ............................................................................................................. 29 figure 19: off_req interface circuit ................................................................................................... 29 figure 20: 32 - pin qfn package dimensions ......................................................................................... 30 tables table 1: 73S8009C pin definitions .......................................................................................................... 7 table 2: absolute maximum device ratings .......................................................................................... 10 table 3: recommended operating conditions ....................................................................................... 11 table 4: dc smart card interface requirements ................................................................................... 11 table 5: digital signals characteristics .................................................................................................. 14 table 6: dc characteristics ................................................................................................................... 15 table 7: voltage / temperature fault det ection circuits ......................................................................... 15 table 8: thermal characteristics ........................................................................................................... 15 table 9: order numbers and packaging marks ...................................................................................... 31
73S8009C data sheet ds_8009c_025 6 rev. 1.5 1 pinout the 73S8009C is supplied as a 32 - pin qfn package. figure 2 : 73s8009 c 32- pin qfn pinout 6 7 8 9 5 4 3 2 1 17 18 19 20 24 23 22 21 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 l i n v p c rdy p r e s i / o on _ off vbus g n d v d d rstin o f f _ a c k aux 2 aux 1 gnd c l k rst vcc v p teridian 73 s 8009 c t e s t 1 clkin v b a t aux 2 uc aux 1 uc i / ouc c s p r e s cmdvcc 5 cmdvcc 3 o f f _ r e q t e s t 2 g n d o f f
ds_8009c_025 73S8009C data sheet rev. 1.5 7 table 1 describes the pin functions for the device. table 1 : 73S8009C pin definitions pin name pin (qfn32) type equivalent circuit description card interface i/o 22 io figure 16 card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 21 io figure 16 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 20 io figure 16 aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 18 o figure 15 card reset: provides reset (rst) signal to card. rst is the pass through signal on rstin. internal control logic will hold rst low when card is not activated or vcc is too low. clk 16 o figure 14 card clock: provides clock signal (clk) to card. clk is the pass through of the signal on pin clkin. internal control logic will hold clk low when card is not activated or vcc is too low. pres 14 i figure 18 card presence switch: active high indicates card is present. should be tied to gnd when not used, but it includes a high - impedance pull - down current source. pres 13 i figure 18 card presence switch: active low indicates card is present. should be tied to v dd when not used, but it includes a high - impedance pull - up current source. vcc 19 pso figure 13 card power supply ? logically controlled by sequencer, output of ldo regulator. requires an external 0.47 f low esr filter capacitor to gnd. gnd 17 gnd ? card ground. miscellaneous inputs and outputs clkin 7 i figure 18 clock sig nal source for the card clock. test1 10 ? ? factory test pin. this pin must be tied to gnd in typical applications . test2 30 ? ? factory test pin. this pin must be tied to gnd in typical applications . power supply and ground vdd 29 pso figure 13 system interface supply voltage and supply voltage for companion controller circuitry. requires a minimum of two 0.1 f capacitors to ground for proper decoupling. vpc 26 psi figure 13 power supply source for main voltage converter circuit. a 10 f and a 0.1 f ceramic capacitor must be connected to this pin. vbat 25 alterna te power source input, typically from two series cells, v > 4 v .
73S8009C data sheet ds_8009c_025 8 rev. 1.5 pin name pin (qfn32) type equivalent circuit description vbus 23 alternate power source in put from usb connector or hub. lin 27 psi figure 13 connection to 10 h inductor for internal step up converter. note: inductor must be rated for 400 ma maximum peak current. vp 15 pso figure 13 intermediate output of main converter circuit. requires an external 4.7 f low esr filter capacitor to gnd. gnd 28,31 ? ground . microcontroller interface cs 12 i figure 18 when cs = 1, the control and signal pins are configured normally. when cs is set low, cmdvcc% , rstin, and cmdvcc# are latched. i / ouc, aux1uc, and aux2uc are set to high - impedance pull - up mode and do not pass data to or from the smart card. signals rdy and off are disabled to prevent a low output and the internal pull - up resistors are disconnected. off 32 o figure 12 interru pt signal to the processor. active low - multi - function indicating fault conditions and card presence. open drain output configuration ? it includes an internal 20 k pull - up to v dd. pull - up is disabled in power down state and cs = 0 modes. i/ouc 1 io figure 17 system controller data i/o to/from the card. includes a pull - up resistor to v dd. aux1uc 2 io figure 17 system controller auxiliary data i/o to/from the card. inc ludes a pull - up resistor to v dd. aux2uc 3 io figure 17 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd. cmdvcc % cmdvcc # 4 5 i i f igure 18 logic low on one or both of these pins will cause the ldo to ramp the vcc supply to the smart card and smart card interface to the value described in the following table . cmdvcc % cmdvcc # vcc output voltage 0 0 1.8 v 0 1 5.0 v 1 0 3.0 v 1 1 ldo off note: see the description of the card power supply for more detail on the operation of cmdvcc% and cmdvcc# . rstin 6 i figure 18 reset input: this signal is the reset command to the card. rdy 8 figure 12 signal to controller indicating the 73S8009C is ready because v cc is above the required value after cmdvcc% and/or cmdvcc# is asserted low. a 20 k ? pull - up resistor to v dd is provided internally. pull - up is disabled in power down state and cs=0 modes.
ds_8009c_025 73S8009C data sheet rev. 1.5 9 pin name pin (qfn32) type equivalent circuit description on_off 24 i figure 11 power control pin. connected to normally open spst switch to ground. closing switc h for duration greater than de - bounce period will turn 73S8009C circuit ?on.? if 73S8009C is ?on,? closing switch will turn 73S8009C to ?off? state after the de - bounce period and off_req/off_ack handshake. off_req 11 o figure 19 digital output. request to the host system controller to turn the 73S8009C off. if on_off switch is closed (to ground) for de - bounce duration and circuit is ?on,? off_req will go high (request to turn off). connected to off_ack via 100 k ? internal resistor. off_ack 9 i figure 18 setting off_ack high will power ?off? all analog functions and disconnect the 73S8009C from v bat or v pc . the pin has an internal 100 k ? resistor connection to off_req so that when not connected or no host interaction is required, the acknowledge will be true and the circuit will turn ?off? immediately with off_req.
73S8009C data sheet ds_8009c_025 10 rev. 1.5 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommended op erating conditions ? smart card interface requirements ? digital signals characteristics ? voltage / temperature fault detection circuits ? thermal characteristics 2.1 absolute maximum ratings table 2 lists the maximum operating conditions f or the 73S8009C . permanent device damage may occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. the smart card interface pins are protected against short circuits to v cc , ground, and each other. table 2 : absolute maximum device ratings parameter rating supply voltage v bus - 0.5 to 6.6 vdc supply voltage v bat - 0.5 to 6.6 vdc supply voltage v pc - 0.5 to 6.6 vdc v dd - 0.5 to 4.0 vdc input voltage for digital inputs - 0.3 to (v dd +0.5) vdc storage temperature - 60 to 150c pin voltage (except card interface) - 0.3 to (v dd + 0.5) vdc pin voltage (card interface) - 0.3 to (v cc + 0.3) vdc pin voltage, lin pin 0.3 to 6.5 vdc esd tol erance ? card interface pins +/ - 6 kv esd tolerance ? other pins +/ - 2 kv pin current , except lin 200 ma pin current, lin + 500 ma in, - 200 ma out note: esd testing on smart card pins is hbm condition, 3 pulses, each p olarity referenced to ground. note: smart card pins are protected against shorts between any combinations of smart card pins.
ds_8009c_025 73S8009C data sheet rev. 1.5 11 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3 . table 3 : recommended operating conditions parameter rating supply voltage v pc 2.7 to 6.5 vdc supply voltage v bus 4.4 to 5.5 vdc supply voltage v bat 4.0 to 6.5 vdc ambient operating temperature - 40 c to +85 c 2.3 smart card interface requirements table 4 lists the 73S8009C smart card interface requirements. table 4 : dc smart card interface requirements symbol parameter condition min nom max unit card power supply (v cc ) regulator general conditions: - 40c < 85c, 2.7 v < v pc < 6.6 v v cc card supply voltage including ripple and noise inactive mode - 0.1 ? 0.1 v inactive mode i cc = 1 ma - 0.1 ? 0.4 v active mode; i cc <65 ma ; 5 v 4.65 ? 5.25 v active mode; i cc < 65 ma ; 3 v 2.85 ? 3.15 v active mode; i cc < 40 ma ; 1.8 v 1.68 ? 1.92 v active mode; single pulse of 100 ma for 2 s; 5 v , fixed load = 25 ma 4.6 ? 5.25 v active mode; single pulse of 100 ma for 2 s; 3 v, fixed load = 25 ma 2.76 ? 3.15 v active mode; current pulses of 40nas with peak |i cc | <200 ma , t <400 ns; 5 v 4.6 ? 5.25 v active mode; current pulses of 40nas with peak |i cc | <200 ma , t <400 ns; 3 v 2.7 ? 3.15 v active mode; current pulses of 20nas with peak |i cc | < 100 ma , t <400 ns; 1.8 v 1.62 ? 1.92 v v ccrip v cc ripple f ripple = 20 khz ? 200 mhz ? 350 mv i ccmax card supply output current static load current, v cc >1.65 ? 40 ma static load current, v cc >4.6 or 2.7 volts as selected ? 65 ma i ccf i cc fault curre nt class a, b (5 v and 3 v) 75 ? 150 ma class c (1.8 v) 55 ? 130 ma i sc maximum current prior to shut - down load current limit prior to vcc shut - down 80 ? 150 ma load current limit pri or to vcc shut - down for vcc=1.8 v 60 ? 130 ma v s vcc slew rate, r ise and fall c = 0.5 f 0.10 0.30 0.70 v/s
73S8009C data sheet ds_8009c_025 12 rev. 1.5 v rdy vcc ready voltage (rdy = 1) 5 v operation, vcc rising 4.6 ? ? v 3 v operation, vcc rising 2.75 ? ? v 1.8 v operation, vcc rising 1.65 ? ? v v ccf rdy = 0 (v cc voltage supervisor threshold) v cc = 5 v ? ? 4.6 v c vpc external filter cap for v pc 8.0 10.0 12.0 f cvp external filter cap for vp 2.0 4.7 6.8 f c f external filter capacitor (v cc to gnd) c f should be ceramic with low esr (<100 m ? ). 0.2 0.47 1.0 f c vdd vdd filter capacitor 0.2 ? 1.0 f ivpcoff vpc supply current for vcc=0 vpc=5 v, vcc=0 v (off) 400 a
ds_8009c_025 73S8009C data sheet rev. 1.5 13 symbol parameter condition min nom max unit interface requirements ? data signals: i/o, aux1, aux2, and host interfaces: i/ouc, aux1uc, aux2uc, dp, dm. i shortl , i shorth , and v inact requirements do not pertain to i/ouc, aux1uc, aux2uc v oh output level, high (i/o, aux1, aux2) i oh =0 0.9 * v cc ? v cc +0.1 v v oh output level, high (i/ouc, aux1uc, aux2uc) i oh = - 40 a 0.75 v cc ? v cc +0.1 v i oh =0 0.9 v dd ? v dd +0.1 v v ol output level, low (i/o, aux1, aux2) i oh = - 40 a 0.75 v dd ? v dd +0.1 v i ol =1 ma ? ? 0.15 *v cc v v ol output level, low (i/ouc, aux1uc, aux2uc) i ol =1 ma ? ? 0.3 v v ih input level, high (i/o, aux1, aux2) 0.6 * v cc ? v cc +0.30 v v ih input level, high (i/ouc, aux1uc, a ux2uc) 0.6 * v dd ? v dd +0.30 v v il input level, low (i/o, aux1, aux2) - 0.15 ? 0.2 * v cc v v il input level, low (i/ouc, aux1uc, aux2uc) - 0.15 ? 0.2 * v dd v v in act output voltage when outside of session i ol = 0 ? ? 0.1 v i ol = 1 ma ? ? 0.3 v i leak i nput leakage v ih = v cc ? ? 10 a i il input current, low (i/o, aux1, aux2) v il = 0 ? ? 0.65 ma i il input current, low (i/ouc, aux1uc, aux2uc) v il = 0 ? ? 0.7 ma i shortl short circuit output current for output low, shorted to v cc through 33 ? ? ? 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? ? ? 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl=50pf, 10% to 90%. ? ? 100 ns t ir , t if input rise, fall times ? ? 1 s r pu internal pull - up resistor output stable for >200ns 8 11 14 k ? fd max maximum data rate ? ? 1 mhz t fd io delay, i/o to i/ouc, aux1 to aux1uc, aux2 to aux2uc,i/ouc to i/o, aux1uc to aux1, aux2uc to aux2 (respectivel y falling edge to falling edge and rising edge to rising edge) edge from master to slave, measured at 50% 60 100 200 ns t rd io ? 15 ? ns c in input capacitance ? ? 10 pf
73S8009C data sheet ds_8009c_025 14 rev. 1.5 symbol parameter condition min nom max unit reset and clock for card interface, rst, clk v oh output level, high i oh = - 200 a 0.9 * v cc ? v cc v v ol output level, low i ol =200 a 0 ? 0.15 *v cc v v in act output voltage when outside of session i ol = 0 ? ? 0.1 v i rst_lim output current limit, rst ? ? 30 ma i clk_lim output current limi t, clk ? ? 70 ma t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% ? ? 12 ns c l = 200pf for rst, 10% to 90% ? ? 100 ns duty cycle for clk c l =35pf, f clk 20 mhz, clkin duty cycle is 48% to 52%. 45 ? 55 % 2.4 digital signals characteristics table 5 lists the 73s8009 c digital signals characteristics. table 5 : digital signals characteristics symbol parameter condition min nom max unit digital i/o (except for i/ouc, aux1uc, aux2uc; see smart card interface requirements for those specifications) v il input low voltage - 0.3 ? 0.8 v vil offack input low voltage for off_ack pin off_req p in = vdd - 0.3 ? 0.7 v v ih input high voltage 1.8 ? v dd + 0.3 v v ol output low voltage i ol = 2 ma ? 0.45 v v oh output high voltage i oh = - 1 ma v dd - 0.45 ? v r out pull - up resistor; off, rdy 14 20 26 k ? r ack resistor between off_req and 0ff_ack 70 100 130 k ? | i il1 | input leakage current gnd < v in < v dd ? ? 5 a t sl time from cs goes high to interface active 50 ? ? ns t dz time from cs goes low to interface inactive, hi - z 50 ? ? ns t is set - up time , control signals to cs rising edge 50 ? ? ns t si hold time, control signals from cs rising edge ? ? 50 ns t id set - up time, control signals to cs fall 50 ? ? ns t di hold time, control signals from cs fall ? ? 50 ns
ds_8009c_025 73S8009C data sheet rev. 1.5 15 2.5 dc characteristics table 6 lists the dc characteristics. table 6 : dc characteristics symbol parameter condition min nom max unit v dd v dd supply voltage 2.7v < vpc < 6.5v, i vddext < 40 ma . 3.0 3.3 3.6 v i ddext v dd current to external l oad ? ? 40 ma i vpc supply current vpc = 2.7v, v cc off, i dd = 0 ? 1.7 ? ma vpc = 3.3v, v cc off, i dd = 0 ? 1.1 ? ma vpc = 5.0v, v cc off, i dd = 0 ? 0.7 ? ma off mode ? 0.01 1 a vbus on vbus detection threshold v dd =3.3 v 3.5 3.9 4.3 v vbus idis vb us discharge current 0.5 1.0 3 ma vbus st by vbus standby current 370 500 a 2.6 voltage / temperature fault detection circuits table 7 lists the voltage / temperature fault detection circuits. table 7 : v oltage / temperature fault detection circuits symbol parameter condition min nom max unit iv p max v p over - current fault ? ? 150 ma i ccf card overcurrent fault 80 ? 150 ma i ccf1p8 card overcurrent fault v cc = 1.8 v 60 ? 130 ma 2.7 thermal characteristics table 8 lists the thermal characteristics. table 8 : thermal characteristics symbol parameter condition min nom max unit tj junction temperature ? ? 125 c ja thermal resistance, junction - to - ambient ? 70 ? c/w jc thermal resistance, junction - to - case ? 6 ? c/w
73S8009C data sheet ds_8009c_025 16 rev. 1.5 3 applications information this section provides general usage information for the design and implementation of the 73S8009C . the documen ts listed in related documentation provide more detailed information. 3.1 example 73S8009C schematics figure 3 shows a typical application schematic for the implementation of the 73s8009 c with a main system switch . note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact teridian for the latest information.
ds_8009c_025 73S8009C data sheet rev. 1.5 17 clkin _ from _ uc c 1 0 . 47 f , off _ ack _ from _ uc off _ interrupt _ to _ uc clk track should be routed far from rst , i / o , c 4 and c 8 notes : 1) vbus = 4. 5 v to 5. 5 v dc . 2) vpc = 2. 7 v to 6. 5 v dc ( should only be used when v bat and v bus are unused ) 3) vbat = 4. 0 v to 6. 5 v dc . 4) internal pull - up allows it to be left open if unused . i / ouc _ to / from _ uc card detection switch is normally closed vdd aux 1 uc _ to / from _ uc aux 2 uc_ to / from _ uc rstin _ from _ uc low esr (< 100 m ? ) should be placed near the sc connecter contact cs _ from _ uc cmdvcc % _ from _ uc r 2 20k smart card connector 1 2 3 4 5 6 7 8 9 1 0 vc c r st c l k c 4 g n d vpp i / o c 8 s w -1 s w -2 see note 4 cmdvcc # _ from _ uc rdy _ status _ to _ uc c 3 see note 2 off _ req _ to _ uc 0 c 2 4 . 7 f c 4 27 pf c 5 27pf see note 5 5) resistor footpring is included in case some filtering is needed on clk vp c 1 2 1 0 1 1 1 3 1 5 1 6 1 4 32 qfn 73 s 80009 c 1 2 3 4 5 6 7 8 c s t est 1 gnd vpc clkin aux 2 rdy pr es pr es i / o aux 1 vbus c l k rst vcc t est 2 cmdvcc % rstin vd d g n d o f f aux 2 uc aux 1 uc i / ouc cmdvcc # vp o f f _ ac k o f f _ r eq on / off vbat l i n g n d 17 18 19 20 21 23 24 22 9 2 8 2 7 2 5 2 6 3 2 3 1 2 9 3 0 vbat 10 f 10 h vdd vbus pushbutton switch sw 1 see note 3 see note 1 vdd _ supply _ to _ uc see note 6 see note 6 6) capacitors c 4 and c 5 are provisional and their footprints should be added for added noise rejection if necessary . 7) inductor must be rated for 400 ma maximum peak current . see note 7 8) v dd - 3. 3v , +/ - 0. 3v , 40 ma max . requires min two 0. 1 f caps to gnd ) see note 8 c 6 0 . 1 f figure 3 : typical 73S8009C applicat ion schematic
73S8009C data sheet ds_8009c_025 18 rev. 1.5 3.2 power supply and converter the power supply and converter circuit takes power from any one of three sources; v pc , v bus , and v bat . v pc is specified to range from 2.7 to 6.5 volts and would typically be supplied by a single cell battery with a voltage range of 2.7 to approximately 3.1 volts. v pc is also appropriate for system supplies of 3.3 or 5 volts. v bus is typically supplied by a connected usb cable and ranges in value from 4.5 to 5.5 volts (6.5 v maximum). v bat is expected to be supp lied from a battery of two series connected cells with a voltage value of 4.0 v to 6.5 v . v bat and v bus are connected to v pc by two fet switches configured as a n spdt switch (break - before - make). they are not enabled at the same time. v bus is automatical ly selected in lieu of v bat when v bus is present. if v pc is provided and v bat or v bus are also used, the source of v pc must be diode isolated from the v pc pin to prevent current flow from v bat or v bus into the v pc source. the power supplied to the v pc is up - converted to the voltage v p utilizing an inductive, step - up converter. a series power inductor (nominal value = 10 h) is connected from v pc to lin, and a 10 f filter capacitor plus a 0.1 f capacitor must be connected to v pc . v p requires a 4.7 f f ilter capacitor and will have a nominal value of 5.5 v during normal operation. v p is used by the smartcard interface circuits (clk, rst, io, aux1, and aux2) and is the source of the regulated smart card supply v cc . v cc can be programmed for values of 5 v, 3 v, and 1.8 v. v dd is also produced from v p . v dd is used by the 73S8009C circuit for logic, input/output buffering, and analog functions as well as being capable of supplying up to 40 ma of current to external devices. figur e 4 shows the block diagram of the 73S8009C. 3.3 power on/off when no power is applied to the v bus pin, a power on/off function is provided such that the circuit will be inoperative during the ?off? state, consuming minimum current from v pc and v bat . if v bus power is supplied, the functions of the on/off switch and circuitry are overridden and the 73S8009C is in the ?on? state with v p and v dd available. without v bus applied, and in the off state, the circuit responds only to the on _ off pin. the on _ off pin shall be connected to a spst switch to ground. if the circuit is off and the switch is closed for a de - bounce period of 50 - 100ms, the circuit shall go into the ?on? state wherein all functions are operating in normal fashion. if the circuit is in the ?on ? state and the on _ off pin is connected to ground for a period greater than the de - bounce period, off_req will be asserted high and held. typically, the off_req signal is presented to a host controller that will assert off_ack high when it has completed a ll shutdown activities. when off_ack is set high, the circuit will de - activate the smart card interface if required and turn off all analog functions and the v dd supply for the logic and companion circuits. the off_ack pin is connected internally to off_ req with a resistor such that if off_ack is unconnected, the action of off_req will assert off_ack high. in this configuration, the circuit shall go into the ?off? state immediately upon off_req = 1. the default state upon application of power is the ?of f? state unless power is supplied to the v bus supply. note that at any time, the controller may assert off_ack and the 73S8009C will go into the ?off? state (when v bus is not present.) if power is applied to both v bat and v bus , the circuit will automatic ally consume power from only the v bus source. the circuit will be unconditionally ?on? when v bus is applied. if the v bus source is removed, the circuit will switchover to the vbat input supply and remain in the ?on? state. the controller circuit firmwar e is required to assert off_ack based on no activity or v bus removal to reduce battery power consumption. when operating from v bus , and not calling for v cc , the step - up converter becomes a simple switch connecting v bus to v p in order to save power. this condition is appropriate for the usb ?suspend? state. the usb ?suspend? state requires the power supply current to be less than 500 a. in order to obtain and meet this low current limitation, the companion controller must be configured into a power - down condition using less than 20 a from v dd . note: when using the vbus input as the sole power source for an ?always on? configuration (on_off input not used), the off_ack and on_off inputs must be connected to ground.
ds_8009c_025 73S8009C data sheet rev. 1.5 19 v pc v dd v b a t 3 . 5 v ref v cc l in on / off off _ req off _ ack rdy cmdvcc # cmdvcc % delay circuit 3.3 v regulator cs v cc regulator linear / dc - dc converter v 1 . 8 t h r e f v 3 . 0 t h r e f v 5 . 0 t h r e f analog mux v p debounce and latch on off v p shutdown v b u s + - + - 10 f 0 . 47 f 4 . 7 f 10 uh i/o rst clk aux 1 aux 2 i/ ouc rstin clkin aux 1 uc aux 2 uc card supply / control logic pres pres gnd gnd gnd off card i/o buffer and signal logic 100 k 0 . 1 f 0 . 1 f 0 . 1 f figure 4 : 73S8009C logical block diagram
73S8009C data sheet ds_8009c_025 20 rev. 1.5 3.4 system controller interface four separate digital inputs and two outputs allow direct control of the card interface from the host: ? pin cs: chip select control. ? pin cmdvcc# and/or cmdvcc% : when low, starts an activation sequence. ? pin rstin: controls the card rst signal. ? pin rdy: indicates when smart card power supply is stable and ready. ? pin off : indicator of card presence and any card fault conditions. interrupt output to the host: when the card is not activated, the off pin informs the host about the card presence only (low = no card in the reader, high = card inserted). whe n cmdvcc ( #/% signals) is/are set low (card activation sequence requested from the host), low level on off means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over - current fault) that automatically initiat es a deactivation sequence. the smart card pass through signals are enabled when the rdy conditions are met. 3.5 card power supply and voltage supervision the 73S8009C smart card interface ic incorporates an ldo voltage regulator for the card power supply, v cc (v p to v cc conversion uses an internal ldo). the voltage output is controlled by the digital input sequence of cmdvcc# and cmdvcc% . this regu lator is able to provide 1.8v, 3v or 5v card voltage sourced from the v p power supply. internal digital circu itry is also powered by the v p power supply (except for the on/off circuitry which is powered from v pc ). a card deactivation sequence is forced upon fault detected by an overcurrent condition or card removal event. the voltage regulator can provide a car d current of 65 ma in compliance with emv 4.1 for 3 - v and 5 - v cards and 40 ma for 1.8 v cards . the signals cmdvcc# and cmdvcc% control the turn - on, output voltage value, and turn - off of v cc . when either signal is asserted low, v cc will ramp to the select ed value or if both signals are asserted low (within 400ns of each other), v cc will ramp to 1.8 v. these signals are edge triggered. if cmdvcc% is asserted low (to command v cc to be 5 v) and at a much later time (greater than 2 s, typically), cmdvcc# is asserted low, it will be ignored (and vice versa.) at the assertion (low) of either or both cmdvcc ( #/% signals), v cc will rise to the requested value. when v cc rises to an acceptable value, and stays above that value for approximately 20 s, rdy will b e set high. approximately 510 s after the fall of cmdvcc ( #/% ), the circuit will check the see if v cc is at or above the required minimum value (indicated by rdy=1) and if not, will begin an emergency deactivation sequence. during the 510 s time, card removal, or de - assertion of cmdvcc ( #/% ) shall also initiate an emergency deactivation sequence. the circuit provides over - current protection and limits icc to 150 ma , maximum for self - protection. when an over - current condition is sensed, the circuit wil l invoke a de - activation sequence.
ds_8009c_025 73S8009C data sheet rev. 1.5 21 3.6 activation and de - activation sequence the host controller is fully responsible for the activation sequencing of the smart card signals clk, rst, i/o, aux1 and aux2. all these signa ls are held low by the 73S8009C when the card is in the de - activated state. upon card activation (the fall of cmdvcc ( #/% )), all the signa ls are held low by the 73S8009C until rdy goes high. the host should set the signals rstin, i/ouc, clkin, aux1uc and aux2uc low prior to activating the c ard and allow rdy to go high before transitioning any of these signals. in order to initiate activation, the card must be present and off must be high. cmdvcc 5 or cmdvcc 3 vcc i / ouc i / o rdy rstin rst clkin clk ignored ignored ignored i / o, aux 1 , aux 2 , clk , rst are held low until rdy = 1 and cmdvccx = 0 i / o = i / ouc if rdy = 1 clk = clkin if rdy = 1 rst = rstin if rdy = 1 t 1 at t 1 ( 50 s ) , if rdy =0 or overcurrent , circuit will de - activate ( safety feature ) vcc valid figure 5 : activation sequence deactivation is initiated either by the system controller by setting both cmdvcc ( #/% ) high, or automatically in the event of hardware faults or assertion of the off_ack signal. hardware faults are over - current, under - voltage, and card extraction during the session. the host can manage the i/o signals, clkin, rstin, and cmdvcc ( #/% ) to create other de - activation sequences for non - emergency situations. the following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the cmdvcc(x)b high: 1. rst goes low at the end of time t1. 2. de - assert clk at the end of time t2. 3. i/o goes low at the end of time t3. exit reception mode. 4. de - assert internal vcc_on at the end of time t4. after a delay, vcc is de - asserted. note: since the 73S8009C does not control the waveshape of clk (it is determined by the input form the host clkin), there is no guarantee that the duty cycle of the last clk high pulse will conform to duty cycle requirements during an emergency deactivation.
73S8009C data sheet ds_8009c_025 22 rev. 1.5 cmdvcc rst clk i/o vcc_on vcc t1 t2 t3 t4 t5 figure 6 : deactivation sequence 3.7 off and fault detection there are two different cases that the system controller can monitor the off signal: to query regarding the card presence outside card sessions, or fo r fault detection during card sessions. outside a card session: in this condition, cmdvcc ( #/% ) are always high, off is low if the card is not present, and high if the card is present. because it is outside a card session, no fault detection can occur an d it will not act upon the off signal. no deactivation is required during this time. during a card session: cmdvcc# and/or cmdvcc% is always low, and off falls low if the card is extracted or if any fault detection is detected. at the same time that off is set low, the sequencer starts the deactivation process and the host should stop all transitions on the signal lines. figure 7 shows the timing diagram for the signals cmdvcc ( #/% ) , pres, and off during a card session and outs ide the card session. pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 7 : off activity
ds_8009c_025 73S8009C data sheet rev. 1.5 23 3.8 chip selection the cs pin allows multiple circuits to operate in parallel, driven from the same host control bus. when cs is high, the pins rstin, cmdvcc % , cmdvcc# and clkin control the chip as described. the pins i/ouc, aux1uc, and aux2uc have 11 k ? pull - up resistors and operate to transfer data to the smart card via i/o, aux1, and aux2 when the smart card is activated. the signals off and rdy have 20 k ? pull - up resistors. when cs goes low, the states of the pins rstin, cmdvcc% , cmdvcc , and clkin are latched and held internally. the pull - up for pins i/ouc, aux1uc, and aux2uc become a very weak pull - up of approximately 3 a . no transfer of data is possible between i/ouc, aux1uc, aux2uc and the smart - card signals i/o, aux1, and aux2. the signals o ff and rdy are set to high impedance and the internal pull - up resistors of 20 k ? are disconnected. with regard to de - activation, cs does not affect the operation of the fault sensing circuits and card sense input. cs off, i/ouc, aux1uc, aux2uc control signals functional hi-z state hi-z state t sl t dz t is t si t id t di figure 8 : cs timing definitions
73S8009C data sheet ds_8009c_025 24 rev. 1.5 3.9 i/o circuitry and timing the states of the i/o, aux1, and aux2 pins are low after power on reset and they are in high when the activation sequencer turns on the i/o reception state. see the activation and de - activation sequence section for more details on when the i/o reception is enabled. the states of i/ouc, aux1uc, and aux2uc are high after power on reset. within a card session and when the i/o reception state is turned on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected, then both i/o lines return to their neutral state. figure 9 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output. neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 9 : i/o and i/ouc state diagram
ds_8009c_025 73S8009C data sheet rev. 1.5 25 the delay between the i/o signals is shown in figure 10 . i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i/ouc: t i/o_hl = 100ns t i/o_lh = 15ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh = 15ns figure 10 : i/o ? i/ouc delays - timin g diagram
73S8009C data sheet ds_8009c_025 26 rev. 1.5 4 equivalent circuits this section provides illustrations of circuits equivalent to those described in the pinout section. pin esd vpc 24k figure 11 : on_off pin pin vdd strong nfet data from circuit output disable 20k esd figure 12 : open drain type ? off and rdy pin esd to internal circuits figure 13 : power input/output circuit, vdd, lin, vpc, vcc, vp
ds_8009c_025 73S8009C data sheet rev. 1.5 27 clk pin vcc very strong pfet very strong nfet from circuit esd esd figure 14 : smart card clk driver circuit rst pin vcc strong pfet strong nfet from circuit esd esd figure 15 : smart card rst driver circuit
73S8009C data sheet ds_8009c_025 28 rev. 1.5 400ns delay io pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 16 : smart card io, aux1, and aux2 interface circuit 400ns delay uc pin vdd strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 17 : smart card i / ouc, aux1uc and aux2uc interface circuit
ds_8009c_025 73S8009C data sheet rev. 1.5 29 pin vdd ttl to circuit pull-up disable very weak pfet esd very weak nfet pull-down enable esd note: pins cmdvcc% , cmdvcc# , cs have the pull - up enabled. pins rstin, clkin, pres, ext_ rst have the pull - down enabled. pin off_ack has a 100 k resistor connected to pin off_req internally. figure 18 : general input circuit pin vdd strong pfet strong nfet data from circuit to off_ack pad output disable esd esd 100k ohm notes: strong pfet or nfet is approximately 100 . very strong pfet or nfet is approximately 50 . medium strength pfet is approximately 1 k . very weak pfet or nfet is approximately 1 m . the diodes represent esd protection devices that will conduct current if forward biased. figure 19 : off_req interface circuit
73S8009C data sheet ds_8009c_025 30 rev. 1.5 5 mechanical drawing s figure 20 : 32 - pin qfn package dimensions 2 . 5 5 2 . 5 5 top view 1 2 3 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 0.2 min. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 bottom view 1 2 3 0.25 0.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 chamfered 0.30
ds_8009c_025 73S8009C data sheet rev. 1.5 31 6 ordering information table 9 lists the order numbers and packaging marks used to identify 73S8009C products. table 9 : order numbers and packaging marks part description order number packaging mark 73S8009C - 32qfn 32- pin lead - free qfn 73S8009C - 32im/f 73 s8009c 73S8009C - 32qfn 32- pin lead - free qfn tape / reel 73S8009C - 32imr/f 73 s8009c 7 related documentation the foll owing 73S8009C document is available from teridian semiconductor corporation: 73S8009C data sheet 73S8009C demo board user manual 8 contact information for more information about teridian semiconductor products or to check the availability of the 73S8009C , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.t eridian.com .
73S8009C data sheet ds_8009c_025 32 rev. 1.5 revision history revision date description 1.0 2/15 /2007 first publication. 1.1 12/5 /2007 replaced 32 qfn punched with sawn. updated 32qfn package mark. 1.2 1/21/2008 changed the dimension of the bottom view 32 - pin qfn package. 1.3 8 /28 /2009 added pin current, lin to table 2 . added section 2.7, thermal characteristics . added a note to the end of section 3.6 . added section 4, equivalent circuits . added section 7 r elated documentation and section 8 c ontact information section. formatted to new documentation style. mis cellaneous editorial changes. 1.4 1 /5 /2010 changed the name of the ?on/off? pin to ?on_off? throughout the document. in figure 1 , corrected the name of the ?iouc? pin to ?i/ouc?. in table 1 , corrected the off_ack name, pin number and type information. in table 7 , changed ?i ddmax ? to ?i vpmax ?. at the end of section 3.3 , added a note about using v bus input. in section 3.5 , deleted ?a voltage supervisor checks the value of the voltage v cc ? and added ?and 40 ma for 1.8 v cards?. 1.5 2/4 /2010 removed all references to the 20qfn package. added c6 to the schematic in figure 3 . teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. all other trademarks are the property of their respective owners. simplifying system integr ation is a trademark of teridian semiconductor corporation. this data sheet is proprietary to teridian semiconductor corporation (tsc) and sets forth design goals for the described product. the data sheet is subject to change. tsc assumes no obligation regarding future manufacture, unless agreed to in writing. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent in fringement and limitation of liability. teridian semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to verify that a data sheet is current before placing o rders. tsc assumes no liability for applications assistance. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com

▲Up To Search▲

Price & Availability of 73S8009C

	To Download 73S8009C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .